///////////////////////////////////////////////////////////////////////////////
//                                                                            /
// IAR Atmel AVR C/C++ Compiler V4.30F/W32              13/Mar/2008  04:52:01 /
// Copyright 1996-2007 IAR Systems. All rights reserved.                      /
//                                                                            /
//    Source file           =  C:\home\kevin\pub\src\bc100\IAR\PWM.c          /
//    Command line          =  C:\home\kevin\pub\src\bc100\IAR\PWM.c          /
//                             --cpu=tiny861 -ms -o C:\home\kevin\pub\src\bc1 /
//                             00\IAR\Release\Obj\ -D NDEBUG -lCN             /
//                             C:\home\kevin\pub\src\bc100\IAR\Release\List\  /
//                             -lB C:\home\kevin\pub\src\bc100\IAR\Release\Li /
//                             st\ --initializers_in_flash -s9                /
//                             --no_cross_call --no_tbaa                      /
//                             -DENABLE_BIT_DEFINITIONS -e -I "C:\Program     /
//                             Files\IAR Systems\Embedded Workbench           /
//                             4.0\avr\INC\" -I "C:\Program Files\IAR         /
//                             Systems\Embedded Workbench 4.0\avr\INC\CLIB\"  /
//                             --eeprom_size 512 --misrac=5-9,11-12,14,16-17, /
//                             19-21,24-26,29-32,34-35,38-39,42-43,46,50,     /
//                             52-54,56-59,61-62,64-65,68-80,83-84,87-91,     /
//                             94-95,98-100,103-110,112-126                   /
//    Enabled MISRA C rules =  5-9,11-12,14,16-17,19-21,24-26,29-32,34-35,    /
//                             38-39,42-43,46,50,52-54,56-59,61-62,64-65,     /
//                             68-80,83-84,87-91,94-95,98-100,103-110,112-126 /
//      Checked             =  5,7-9,11-12,14,17,19-21,24,29-32,34-35,38-39,  /
//                             42,46,50,52-54,56-59,61-62,64,68-69,71-80,     /
//                             83-84,87-89,91,94-95,98,100,104-105,108-109,   /
//                             112-115,118-126                                /
//      Not checked         =  6,16,25-26,43,65,70,90,99,103,106-107,110,     /
//                             116-117                                        /
//    List file             =  C:\home\kevin\pub\src\bc100\IAR\Release\List\P /
//                             WM.s90                                         /
//                                                                            /
//                                                                            /
///////////////////////////////////////////////////////////////////////////////

        NAME PWM

        RSEG CSTACK:DATA:NOROOT(0)
        RSEG RSTACK:DATA:NOROOT(0)

        PUBLIC PWM_DecrementDutyCycle
        PUBLIC PWM_IncrementDutyCycle
        PUBLIC PWM_Start
        PUBLIC PWM_Stop
        PUBWEAK _A_DDRB
        PUBWEAK _A_DT1
        PUBWEAK _A_OCR1A
        PUBWEAK _A_OCR1B
        PUBWEAK _A_OCR1C
        PUBWEAK _A_OCR1D
        PUBWEAK _A_PLLCSR
        PUBWEAK _A_TCCR1A
        PUBWEAK _A_TCCR1B
        PUBWEAK _A_TCCR1C
        PUBWEAK _A_TCCR1D
        PUBWEAK _A_TCCR1E
        PUBWEAK __?EEARH
        PUBWEAK __?EEARL
        PUBWEAK __?EECR
        PUBWEAK __?EEDR

        EXTERN Time_Set
        EXTERN Time_Left

// C:\home\kevin\pub\src\bc100\IAR\PWM.c
//    1 /* This file has been prepared for Doxygen automatic documentation generation.*/
//    2 /*! \file *********************************************************************
//    3  *
//    4  * \brief
//    5  *      Functions for use of PWM
//    6  *
//    7  *      Contains functions for initializing and controlling PWM output.
//    8  *
//    9  * \par Application note:
//   10  *      AVR458: Charging Li-Ion Batteries with BC100\n
//   11  *      AVR463: Charging NiMH Batteries with BC100
//   12  *
//   13  * \par Documentation
//   14  *      For comprehensive code documentation, supported compilers, compiler 
//   15  *      settings and supported devices see readme.html
//   16  *
//   17  * \author
//   18  *      Atmel Corporation: http://www.atmel.com \n
//   19  *      Support email: avr@atmel.com
//   20  *
//   21  * 
//   22  * $Name$
//   23  * $Revision: 2299 $
//   24  * $RCSfile$
//   25  * $URL: http://svn.norway.atmel.com/AppsAVR8/avr458_Charging_Li-Ion_Batteries_with_BC100/tag/20070904_release_1.0/code/IAR/PWM.c $
//   26  * $Date: 2007-08-23 12:55:51 +0200 (to, 23 aug 2007) $\n
//   27  ******************************************************************************/
//   28 
//   29 #include <ioavr.h>

        ASEGN ABSOLUTE:DATA:NOROOT,050H
// <unnamed> volatile __io _A_TCCR1A
_A_TCCR1A:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,04fH
// <unnamed> volatile __io _A_TCCR1B
_A_TCCR1B:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,04dH
// <unnamed> volatile __io _A_OCR1A
_A_OCR1A:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,04cH
// <unnamed> volatile __io _A_OCR1B
_A_OCR1B:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,04bH
// <unnamed> volatile __io _A_OCR1C
_A_OCR1C:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,04aH
// <unnamed> volatile __io _A_OCR1D
_A_OCR1D:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,049H
// <unnamed> volatile __io _A_PLLCSR
_A_PLLCSR:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,047H
// <unnamed> volatile __io _A_TCCR1C
_A_TCCR1C:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,046H
// <unnamed> volatile __io _A_TCCR1D
_A_TCCR1D:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,044H
// <unnamed> volatile __io _A_DT1
_A_DT1:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,037H
// <unnamed> volatile __io _A_DDRB
_A_DDRB:
        DS 1

        ASEGN ABSOLUTE:DATA:NOROOT,020H
// <unnamed> volatile __io _A_TCCR1E
_A_TCCR1E:
        DS 1
//   30 
//   31 #include "enums.h"
//   32 
//   33 #include "main.h"
//   34 #include "PWM.h"
//   35 #include "time.h"
//   36 
//   37 
//   38 //******************************************************************************
//   39 // Functions
//   40 //******************************************************************************
//   41 /*! \brief Stops PWM output
//   42  *
//   43  */

        RSEG CODE:CODE:NOROOT(1)
//   44 void PWM_Stop(void)
PWM_Stop:
//   45 {
//   46 	OCR1B = 0;  // Reset compare level.
        LDI     R16, 0
        OUT     0x2C, R16
//   47 	PLLCSR = 0; // Disable PLL, switch to synchronous CLK mode.
        OUT     0x29, R16
//   48 	TCCR1A = 0; // Set normal port operation, disable PWM modes.
        OUT     0x30, R16
//   49 	TCCR1B = 0; // Stop timer/counter1.
        OUT     0x2F, R16
//   50 	TCCR1C = 0; // Set normal port operation.
        OUT     0x27, R16
//   51 	TCCR1D = 0; // No fault protection, normal waveform.
        OUT     0x26, R16
//   52 	OCR1C = 0;  // Reset compare.
        OUT     0x2B, R16
//   53 	OCR1D = 0;  // Reset compare.
        OUT     0x2A, R16
//   54 	DT1 = 0;    // No dead time values.
        OUT     0x24, R16
//   55 }
        RET
        REQUIRE _A_TCCR1A
        REQUIRE _A_TCCR1B
        REQUIRE _A_OCR1B
        REQUIRE _A_OCR1C
        REQUIRE _A_OCR1D
        REQUIRE _A_PLLCSR
        REQUIRE _A_TCCR1C
        REQUIRE _A_TCCR1D
        REQUIRE _A_DT1
//   56 
//   57 
//   58 /*! \brief Initializes and starts PWM output
//   59  *
//   60  * Initializes timer1 for use as a PWM with a clock rate of 64 MHz.\n
//   61  * Its comparator is connected to PB3 and will output high until timer1 reaches
//   62  * the value of OCR1B. It is then dropped to 0.\n
//   63  * The comparator outputs high again when the counter overflows, which will
//   64  * happen at a rate of 250 kHz.
//   65  */

        RSEG CODE:CODE:NOROOT(1)
//   66 void PWM_Start(void)
PWM_Start:
//   67 {
//   68 	// Clear OC1B on compare match, enable PWM on comparator OCR1B.
//   69 	TCCR1A = (1<<COM1B1)|(0<<COM1B0)|(1<<PWM1B);
        LDI     R16, 33
        OUT     0x30, R16
//   70 	
//   71 	// Non-inverted PWM, T/C stopped.
//   72 	TCCR1B = 0;
        LDI     R16, 0
        OUT     0x2F, R16
//   73 	
//   74 	// Copy shadow bits, disconnect OC1D.
//   75 	TCCR1C = (TCCR1A & 0xF0);
        IN      R16, 0x30
        ANDI    R16, 0xF0
        OUT     0x27, R16
//   76 	
//   77 	// No fault protection, use phase & frequency correct PWM.
//   78 	TCCR1D = (0<<WGM11)|(1<WGM10);
        LDI     R16, 0
        OUT     0x26, R16
//   79 	
//   80 	// Does not matter -- PWM6 mode not used.
//   81 	TCCR1E = 0;
        OUT     0x00, R16
//   82 	
//   83 	// Does not matter -- OC1A is disabled.
//   84 	OCR1A = 0;
        OUT     0x2D, R16
//   85 	
//   86 	// Set reset compare level. (Offset is used, or JumperCheck() will fail.)
//   87 	OCR1B = PWM_OFFSET;
        LDI     R16, 12
        OUT     0x2C, R16
//   88 	
//   89 	// TOP value for PWM, f(PWM) = 64MHz / 255 = 251kHz.
//   90 	OCR1C = 0xFF;
        LDI     R16, 255
        OUT     0x2B, R16
//   91 	
//   92 	// Does not matter -- OC1D is disabled.
//   93 	OCR1D = 0;
        LDI     R16, 0
        OUT     0x2A, R16
//   94 	
//   95 	// No dead time values.
//   96 	DT1 = 0;
        OUT     0x24, R16
//   97 	
//   98 	// Set PWM port pin to output.
//   99 	DDRB |= (1<<PB3);
        SBI     0x17, 0x03
//  100 	
//  101 	// Enable PLL, use full speed mode.
//  102 	PLLCSR = (0<<LSM) | (1<<PLLE);
        LDI     R16, 2
        OUT     0x29, R16
//  103 	
//  104 	// Use general timer and wait 1 ms for PLL lock to settle.
//  105 	Time_Set(TIMER_GEN,0,0,1);
        LDI     R20, 1
        LDI     R17, 0
        LDI     R18, 0
        LDI     R19, 0
        RCALL   Time_Set
//  106 	do{ 
//  107 	}while(Time_Left(TIMER_GEN));
??PWM_Start_0:
        LDI     R16, 2
        RCALL   Time_Left
        TST     R16
        BRNE    ??PWM_Start_0
//  108 	
//  109 	// Now wait for PLL to lock.
//  110 	do{ 
//  111 	}while((PLLCSR & (1<<PLOCK)) == 0);
??PWM_Start_1:
        IN      R16, 0x29
        SBRS    R16, 0
        RJMP    ??PWM_Start_1
//  112 
//  113 	// Use PLL as clock source.
//  114 	PLLCSR |= (1<<PCKE);
        IN      R16, 0x29
        ORI     R16, 0x04
        OUT     0x29, R16
//  115 	
//  116 	// CLK PCK = 64MHz / 1 = 64MHz.
//  117 	TCCR1B |= (0<<CS13)|(0<<CS12)|(0<<CS11)|(1<<CS10);
        IN      R16, 0x2F
        ORI     R16, 0x01
        OUT     0x2F, R16
//  118 }
        RET
        REQUIRE _A_TCCR1A
        REQUIRE _A_TCCR1B
        REQUIRE _A_OCR1A
        REQUIRE _A_OCR1B
        REQUIRE _A_OCR1C
        REQUIRE _A_OCR1D
        REQUIRE _A_PLLCSR
        REQUIRE _A_TCCR1C
        REQUIRE _A_TCCR1D
        REQUIRE _A_DT1
        REQUIRE _A_DDRB
        REQUIRE _A_TCCR1E
//  119 
//  120 
//  121 /*! \brief Increments the PWM duty cycle, if not already at max
//  122  *
//  123  * \retval TRUE Success, duty cycle could be incremented.
//  124  * \retval FALSE Failure, duty cycle already at maximum.
//  125  */

        RSEG CODE:CODE:NOROOT(1)
//  126 unsigned char PWM_IncrementDutyCycle(void){
PWM_IncrementDutyCycle:
//  127 
//  128 	if (OCR1B < PWM_MAX) {
        IN      R16, 0x2C
        CPI     R16, 255
        BREQ    ??PWM_IncrementDutyCycle_0
//  129 		OCR1B += 1;
        IN      R16, 0x2C
        INC     R16
        OUT     0x2C, R16
//  130 		return(TRUE);
        LDI     R16, 1
        RET
//  131 	} else {
//  132 		return(FALSE);
??PWM_IncrementDutyCycle_0:
        LDI     R16, 0
        RET
        REQUIRE _A_OCR1B
//  133 	}
//  134 }
//  135 
//  136 
//  137 /*! \brief Decrements the PWM duty cycle, if not already at zero.
//  138  *
//  139  * \retval TRUE Success, duty cycle could be decremented.
//  140  * \retval FALSE Failure, duty cycle already at zero.
//  141  */

        RSEG CODE:CODE:NOROOT(1)
//  142 unsigned char PWM_DecrementDutyCycle(void){
PWM_DecrementDutyCycle:
//  143 	
//  144 	if (OCR1B > 0)	{
        IN      R16, 0x2C
        TST     R16
        BREQ    ??PWM_DecrementDutyCycle_0
//  145 		OCR1B -= 1;
        IN      R16, 0x2C
        DEC     R16
        OUT     0x2C, R16
//  146 		return(TRUE);
        LDI     R16, 1
        RET
//  147 	} else {
//  148 		return(FALSE);
??PWM_DecrementDutyCycle_0:
        LDI     R16, 0
        RET
        REQUIRE _A_OCR1B
//  149 	}
//  150 }

        ASEGN ABSOLUTE:DATA:NOROOT,01cH
__?EECR:

        ASEGN ABSOLUTE:DATA:NOROOT,01dH
__?EEDR:

        ASEGN ABSOLUTE:DATA:NOROOT,01eH
__?EEARL:

        ASEGN ABSOLUTE:DATA:NOROOT,01fH
__?EEARH:

        END
// 
//  12 bytes in segment ABSOLUTE
// 142 bytes in segment CODE
// 
// 142 bytes of CODE memory
//   0 bytes of DATA memory (+ 12 bytes shared)
//
//Errors: none
//Warnings: none