############################################################################### # # # IAR Atmel AVR C/C++ Compiler V4.30F/W32 13/Mar/2008 04:52:02 # # Copyright 1996-2007 IAR Systems. All rights reserved. # # # # Source file = C:\home\kevin\pub\src\bc100\IAR\USI.c # # Command line = C:\home\kevin\pub\src\bc100\IAR\USI.c # # --cpu=tiny861 -ms -o C:\home\kevin\pub\src\bc10 # # 0\IAR\Release\Obj\ -D NDEBUG -lCN # # C:\home\kevin\pub\src\bc100\IAR\Release\List\ # # -lB C:\home\kevin\pub\src\bc100\IAR\Release\Lis # # t\ --initializers_in_flash -s9 --no_cross_call # # --no_tbaa -DENABLE_BIT_DEFINITIONS -e -I # # "C:\Program Files\IAR Systems\Embedded # # Workbench 4.0\avr\INC\" -I "C:\Program # # Files\IAR Systems\Embedded Workbench # # 4.0\avr\INC\CLIB\" --eeprom_size 512 # # --misrac=5-9,11-12,14,16-17,19-21,24-26,29-32, # # 34-35,38-39,42-43,46,50,52-54,56-59,61-62, # # 64-65,68-80,83-84,87-91,94-95,98-100,103-110, # # 112-126 # # Enabled MISRA C rules = 5-9,11-12,14,16-17,19-21,24-26,29-32,34-35, # # 38-39,42-43,46,50,52-54,56-59,61-62,64-65, # # 68-80,83-84,87-91,94-95,98-100,103-110,112-126 # # Checked = 5,7-9,11-12,14,17,19-21,24,29-32,34-35,38-39, # # 42,46,50,52-54,56-59,61-62,64,68-69,71-80, # # 83-84,87-89,91,94-95,98,100,104-105,108-109, # # 112-115,118-126 # # Not checked = 6,16,25-26,43,65,70,90,99,103,106-107,110, # # 116-117 # # List file = C:\home\kevin\pub\src\bc100\IAR\Release\List\US # # I.lst # # Object file = C:\home\kevin\pub\src\bc100\IAR\Release\Obj\USI # # .r90 # # # # # ############################################################################### C:\home\kevin\pub\src\bc100\IAR\USI.c 1 /* This file has been prepared for Doxygen automatic documentation generation.*/ 2 /*! \file ********************************************************************* 3 * 4 * \brief 5 * Functions for use of the Universal Serial Interface 6 * 7 * Contains high level functions for initializing the USI as an SPI slave, 8 * interrupt handling, sending and receiving single bytes. 9 * 10 * \par Application note: 11 * AVR458: Charging Li-Ion Batteries with BC100 \n 12 * AVR463: Charging NiMH Batteries with BC100 13 * 14 * \par Documentation: 15 * For comprehensive code documentation, supported compilers, compiler 16 * settings and supported devices see readme.html 17 * 18 * \author 19 * Atmel Corporation: http://www.atmel.com \n 20 * Support email: avr@atmel.com \n 21 * Original author: \n 22 * 23 * $Name$ 24 * $Revision: 2299 $ 25 * $RCSfile$ 26 * $URL: http://svn.norway.atmel.com/AppsAVR8/avr458_Charging_Li-Ion_Batteries_with_BC100/tag/20070904_release_1.0/code/IAR/USI.c $ 27 * $Date: 2007-08-23 12:55:51 +0200 (to, 23 aug 2007) $\n 28 ******************************************************************************/ 29 30 #include \ In segment ABSOLUTE, at 0x38 \ volatile __io _A_PORTB \ _A_PORTB: \ 00000000 DS 1 \ In segment ABSOLUTE, at 0x37 \ volatile __io _A_DDRB \ _A_DDRB: \ 00000000 DS 1 \ In segment ABSOLUTE, at 0x2f \ volatile __io _A_USIDR \ _A_USIDR: \ 00000000 DS 1 \ In segment ABSOLUTE, at 0x2e \ volatile __io _A_USISR \ _A_USISR: \ 00000000 DS 1 \ In segment ABSOLUTE, at 0x2d \ volatile __io _A_USICR \ _A_USICR: \ 00000000 DS 1 31 #include 32 33 #include "enums.h" 34 #include "structs.h" 35 36 #include "main.h" 37 #include "ADC.h" 38 #include "battery.h" 39 #include "time.h" 40 #include "USI.h" 41 42 43 //****************************************************************************** 44 // Variables 45 //****************************************************************************** 46 //! SPI status struct \ In segment NEAR_Z, align 1, keep-with-next \ 00000000 REQUIRE `?` 47 SPI_Status_t SPI; \ SPI: \ 00000000 DS 4 48 49 50 //****************************************************************************** 51 //Functions 52 //***************************************************************************** 53 /*! \brief USI Counter Overflow Interrupt Service Routine 54 * 55 * When the USI counter overflows, a byte has been transferred.\n 56 * The USIDR contents are stored and flags are updated. 57 * 58 * The protocol is quite simple and has three sequential states: command, 59 * address and data. 60 * (Keep in mind that the Master is in charge of data clocking, which means 61 * there is a one byte "delay" from when the Slave puts something to SPI till 62 * the Master can read it.) 63 * 64 * 1. If a non-zero byte is received in the command state, the ISR will 65 * store the commands to the SPI struct (read/write, EEPROM/SRAM, number of 66 * bytes). To signal that the command was received, 0xCC is put to the SPI bus. 67 * If a zero byte (0x00) is received in the command state, it is simply ignored 68 * because it is an invalid command. 69 * 70 * 2. When a byte is received in the address state, it is stored to the SPI 71 * struct. To signal that the address was received, 0xBB is put to SPI bus. 72 * 73 * 3. In the data state, variables are read/written "from back to front" until 74 * the byte counter reaches zero. Since the Master is in charge of the data 75 * clocking, the Slave will go to command state before the last byte is 76 * transferred during reading. This means that the Master should send an 77 * invalid command when getting each byte, ie 0x00. 78 * 79 * If the time between two transfers is 1 second or more, the Slave 80 * automatically reverts to command state. 81 * 82 * \note Battery charging is not automatically halted during SPI communication. 83 * This means that the current charge state (current and voltage) will 84 * remain constant during heavy and prolonged serial traffic. 85 * 86 * \todo Variable writing not implemented yet. 87 * \todo EEPROM/SRAM flag doesn't really do anything with this implementation. 88 */ 89 #pragma vector=USI_OVF_vect \ In segment CODE, align 2, keep-with-next 90 __interrupt void USI_OVF_ISR(void) \ USI_OVF_ISR: 91 { \ 00000000 938A ST -Y, R24 \ 00000002 93FA ST -Y, R31 \ 00000004 93EA ST -Y, R30 \ 00000006 923A ST -Y, R3 \ 00000008 922A ST -Y, R2 \ 0000000A 921A ST -Y, R1 \ 0000000C 920A ST -Y, R0 \ 0000000E 937A ST -Y, R23 \ 00000010 936A ST -Y, R22 \ 00000012 935A ST -Y, R21 \ 00000014 934A ST -Y, R20 \ 00000016 933A ST -Y, R19 \ 00000018 932A ST -Y, R18 \ 0000001A 931A ST -Y, R17 \ 0000001C 930A ST -Y, R16 \ 0000001E B78F IN R24, 0x3F 92 // If the communication timed out, set ST_CMD as current state. 93 if (!Time_Left(TIMER_USI)) { \ 00000020 E000 LDI R16, 0 \ 00000022 .... RCALL Time_Left \ 00000024 2300 TST R16 \ 00000026 F431 BRNE ??USI_OVF_ISR_0 94 SPI.State = ST_CMD; \ 00000028 .... LDI R30, LOW(SPI) \ 0000002A .... LDI R31, (SPI) >> 8 \ 0000002C 8102 LDD R16, Z+2 \ 0000002E 730F ANDI R16, 0x3F \ 00000030 6400 ORI R16, 0x40 \ 00000032 8302 STD Z+2, R16 95 } 96 97 // Start communication timer. If further communication doesn't happen 98 // within 1 second, the SPI communication state is reset to CMD. 99 Time_Set(TIMER_USI, 0, 1, 0); \ ??USI_OVF_ISR_0: \ 00000034 E040 LDI R20, 0 \ 00000036 E011 LDI R17, 1 \ 00000038 E020 LDI R18, 0 \ 0000003A E030 LDI R19, 0 \ 0000003C E000 LDI R16, 0 \ 0000003E .... RCALL Time_Set 100 101 // Clear USI counter and flag completed transfer. 102 USISR = (1<> 8 \ 00000048 8103 LDD R16, Z+3 \ 0000004A 6004 ORI R16, 0x04 \ 0000004C 8303 STD Z+3, R16 104 105 // Process incoming data. 106 switch(SPI.State) { \ 0000004E 8112 LDD R17, Z+2 \ 00000050 2F01 MOV R16, R17 \ 00000052 0F00 LSL R16 \ 00000054 1F00 ROL R16 \ 00000056 1F00 ROL R16 \ 00000058 7003 ANDI R16, 0x03 \ 0000005A 5001 SUBI R16, 1 \ 0000005C F029 BREQ ??USI_OVF_ISR_1 \ 0000005E 950A DEC R16 \ 00000060 F101 BREQ ??USI_OVF_ISR_2 \ 00000062 950A DEC R16 \ 00000064 F131 BREQ ??USI_OVF_ISR_3 \ 00000066 C072 RJMP ??USI_OVF_ISR_4 107 // A valid SPI transfer starts with a Command Byte sent by the Master. 108 case ST_CMD: 109 SPI.Data = USIDR; // Store the transferred byte. \ ??USI_OVF_ISR_1: \ 00000068 B10F IN R16, 0x0F \ 0000006A 8300 ST Z, R16 110 111 // If the master sent 0, it is trying to get data. Ignore in this state. 112 if (SPI.Data != 0) { \ 0000006C 2300 TST R16 \ 0000006E F409 BRNE $+2+2 \ 00000070 C06D RJMP ??USI_OVF_ISR_4 113 // Does the master want to read or write? 114 if (SPI.Data & 0x40) { \ 00000072 FF06 SBRS R16, 6 \ 00000074 C003 RJMP ??USI_OVF_ISR_5 115 SPI.Read = FALSE; \ 00000076 8103 LDD R16, Z+3 \ 00000078 7F0E ANDI R16, 0xFE \ 0000007A C002 RJMP ??USI_OVF_ISR_6 116 } else { 117 SPI.Read = TRUE; \ ??USI_OVF_ISR_5: \ 0000007C 8103 LDD R16, Z+3 \ 0000007E 6001 ORI R16, 0x01 \ ??USI_OVF_ISR_6: \ 00000080 8303 STD Z+3, R16 118 } 119 120 // From/to EEPROM or SRAM? 121 if (SPI.Data &0x80) { \ 00000082 8100 LD R16, Z \ 00000084 FF07 SBRS R16, 7 \ 00000086 C003 RJMP ??USI_OVF_ISR_7 122 SPI.EEPROM = TRUE; \ 00000088 8103 LDD R16, Z+3 \ 0000008A 6002 ORI R16, 0x02 \ 0000008C C002 RJMP ??USI_OVF_ISR_8 123 } else { 124 SPI.EEPROM = FALSE; \ ??USI_OVF_ISR_7: \ 0000008E 8103 LDD R16, Z+3 \ 00000090 7F0D ANDI R16, 0xFD \ ??USI_OVF_ISR_8: \ 00000092 8303 STD Z+3, R16 125 } 126 127 SPI.Count = (SPI.Data & 0x3F); // Get number of bytes to receive/send. 128 SPI.State = ST_ADDR; // The Master will send the address byte next. \ 00000094 8100 LD R16, Z \ 00000096 730F ANDI R16, 0x3F \ 00000098 6800 ORI R16, 0x80 \ 0000009A 8302 STD Z+2, R16 129 130 SPI_Put(0xCC); // Signal that command was received. \ 0000009C EC0C LDI R16, 204 \ ??USI_OVF_ISR_9: \ 0000009E .... RCALL SPI_Put \ 000000A0 C055 RJMP ??USI_OVF_ISR_4 131 } 132 break; 133 134 135 case ST_ADDR: 136 SPI.Data = USIDR; // Store the address. \ ??USI_OVF_ISR_2: \ 000000A2 B10F IN R16, 0x0F \ 000000A4 8300 ST Z, R16 137 SPI.Address = SPI.Data; \ 000000A6 8301 STD Z+1, R16 138 SPI.State = ST_DATA; // The master will send/wait for data next. \ 000000A8 2F01 MOV R16, R17 \ 000000AA 6C00 ORI R16, 0xC0 \ 000000AC 8302 STD Z+2, R16 139 140 SPI_Put(0xBB); // Signal that address was received. \ 000000AE EB0B LDI R16, 187 \ 000000B0 CFF6 RJMP ??USI_OVF_ISR_9 141 break; 142 143 144 // Note well: this will process at least one byte, regardless of Count. 145 case ST_DATA: 146 if (SPI.Count-- > 0) { \ ??USI_OVF_ISR_3: \ 000000B2 2F21 MOV R18, R17 \ 000000B4 7C10 ANDI R17, 0xC0 \ 000000B6 2F02 MOV R16, R18 \ 000000B8 950A DEC R16 \ 000000BA 730F ANDI R16, 0x3F \ 000000BC 2B01 OR R16, R17 \ 000000BE 8302 STD Z+2, R16 \ 000000C0 732F ANDI R18, 0x3F \ 000000C2 F409 BRNE $+2+2 \ 000000C4 C040 RJMP ??USI_OVF_ISR_10 147 // Write specified variable to SPI, "back to front". 148 if (SPI.Read) { \ 000000C6 8121 LDD R18, Z+1 \ 000000C8 8113 LDD R17, Z+3 \ 000000CA FF10 SBRS R17, 0 \ 000000CC C02E RJMP ??USI_OVF_ISR_11 149 switch (SPI.Address) { \ 000000CE 952A DEC R18 \ 000000D0 F049 BREQ ??USI_OVF_ISR_12 \ 000000D2 952A DEC R18 \ 000000D4 F071 BREQ ??USI_OVF_ISR_13 \ 000000D6 952A DEC R18 \ 000000D8 F091 BREQ ??USI_OVF_ISR_14 \ 000000DA 952A DEC R18 \ 000000DC F0B1 BREQ ??USI_OVF_ISR_15 \ 000000DE 952A DEC R18 \ 000000E0 F0E1 BREQ ??USI_OVF_ISR_16 \ 000000E2 C021 RJMP ??USI_OVF_ISR_17 150 case ADR_ADCS: 151 SPI_Put(*(((unsigned char*)&ADCS) + (SPI.Count))); \ ??USI_OVF_ISR_12: \ 000000E4 730F ANDI R16, 0x3F \ 000000E6 E010 LDI R17, 0 \ 000000E8 01F8 MOVW R31:R30, R17:R16 \ 000000EA .... SUBI R30, LOW((-(ADCS) & 0xFFFF)) \ 000000EC .... SBCI R31, (-(ADCS) & 0xFFFF) >> 8 \ ??USI_OVF_ISR_18: \ 000000EE 8100 LD R16, Z \ 000000F0 CFD6 RJMP ??USI_OVF_ISR_9 152 break; 153 154 155 case ADR_BATTACTIVE: 156 SPI_Put(*((unsigned char*)&BattActive + (SPI.Count))); \ ??USI_OVF_ISR_13: \ 000000F2 730F ANDI R16, 0x3F \ 000000F4 E010 LDI R17, 0 \ 000000F6 01F8 MOVW R31:R30, R17:R16 \ 000000F8 .... SUBI R30, LOW((-(BattActive) & 0xFFFF)) \ 000000FA .... SBCI R31, (-(BattActive) & 0xFFFF) >> 8 \ 000000FC CFF8 RJMP ??USI_OVF_ISR_18 157 break; 158 159 160 case ADR_BATTDATA: 161 SPI_Put(*((unsigned char*)&BattData + (SPI.Count))); \ ??USI_OVF_ISR_14: \ 000000FE 730F ANDI R16, 0x3F \ 00000100 E010 LDI R17, 0 \ 00000102 01F8 MOVW R31:R30, R17:R16 \ 00000104 .... SUBI R30, LOW((-(BattData) & 0xFFFF)) \ 00000106 .... SBCI R31, (-(BattData) & 0xFFFF) >> 8 \ 00000108 CFF2 RJMP ??USI_OVF_ISR_18 162 break; 163 164 165 case ADR_BATTCTRL: 166 SPI_Put(*((__eeprom unsigned char*)&BattControl + (SPI.Count))); \ ??USI_OVF_ISR_15: \ 0000010A 730F ANDI R16, 0x3F \ 0000010C E010 LDI R17, 0 \ 0000010E .... LDI R20, LOW(BattControl) \ 00000110 .... LDI R21, (BattControl) >> 8 \ 00000112 0F40 ADD R20, R16 \ 00000114 1F51 ADC R21, R17 \ 00000116 .... RCALL __eeget8_16 \ 00000118 CFC2 RJMP ??USI_OVF_ISR_9 167 break; 168 169 case ADR_TIMERS: 170 SPI_Put(*((unsigned char*)&timeval + (SPI.Count))); \ ??USI_OVF_ISR_16: \ 0000011A 730F ANDI R16, 0x3F \ 0000011C E010 LDI R17, 0 \ 0000011E 01F8 MOVW R31:R30, R17:R16 \ 00000120 .... SUBI R30, LOW((-(timeval) & 0xFFFF)) \ 00000122 .... SBCI R31, (-(timeval) & 0xFFFF) >> 8 \ 00000124 CFE4 RJMP ??USI_OVF_ISR_18 171 break; 172 173 174 default: 175 SPI_Put(0); \ ??USI_OVF_ISR_17: \ 00000126 E000 LDI R16, 0 \ 00000128 CFBA RJMP ??USI_OVF_ISR_9 176 break; 177 } 178 } else { 179 // Read byte from SPI 180 SPI.Data = USIDR; \ ??USI_OVF_ISR_11: \ 0000012A B11F IN R17, 0x0F \ 0000012C 8310 ST Z, R17 181 182 // ******************************************** 183 // THIS FUNCTION HAS NOT BEEN FULLY IMPLEMENTED 184 // ******************************************** 185 186 // Save byte to specified variable. 187 switch (SPI.Address) { \ 0000012E 5024 SUBI R18, 4 \ 00000130 F469 BRNE ??USI_OVF_ISR_4 188 case ADR_BATTCTRL: 189 *((__eeprom unsigned char*)&BattControl + SPI.Count) = SPI.Data; \ 00000132 2F21 MOV R18, R17 \ 00000134 730F ANDI R16, 0x3F \ 00000136 E010 LDI R17, 0 \ 00000138 .... LDI R20, LOW(BattControl) \ 0000013A .... LDI R21, (BattControl) >> 8 \ 0000013C 0F40 ADD R20, R16 \ 0000013E 1F51 ADC R21, R17 \ 00000140 2F02 MOV R16, R18 \ 00000142 .... RCALL __eeput8_16 \ 00000144 C003 RJMP ??USI_OVF_ISR_4 190 break; 191 192 193 default: 194 break; 195 } 196 } 197 198 199 } else { 200 SPI.State = ST_CMD; \ ??USI_OVF_ISR_10: \ 00000146 730F ANDI R16, 0x3F \ 00000148 6400 ORI R16, 0x40 \ 0000014A 8302 STD Z+2, R16 201 } 202 break; 203 204 default: // Shouldn't end up here. (Unknown SPI-state) 205 break; 206 } 207 } \ ??USI_OVF_ISR_4: \ 0000014C BF8F OUT 0x3F, R24 \ 0000014E 9109 LD R16, Y+ \ 00000150 9119 LD R17, Y+ \ 00000152 9129 LD R18, Y+ \ 00000154 9139 LD R19, Y+ \ 00000156 9149 LD R20, Y+ \ 00000158 9159 LD R21, Y+ \ 0000015A 9169 LD R22, Y+ \ 0000015C 9179 LD R23, Y+ \ 0000015E 9009 LD R0, Y+ \ 00000160 9019 LD R1, Y+ \ 00000162 9029 LD R2, Y+ \ 00000164 9039 LD R3, Y+ \ 00000166 91E9 LD R30, Y+ \ 00000168 91F9 LD R31, Y+ \ 0000016A 9189 LD R24, Y+ \ 0000016C 9518 RETI \ 0000016E REQUIRE _A_USIDR \ 0000016E REQUIRE _A_USISR 208 209 210 /*! \brief Initializes USI as an SPI slave 211 * 212 * Initializes USI as a 3-wire SPI slave using the pins specified in USI.h for 213 * I/O and clock, and USI counter overflow interrupts enabled.\n 214 * Also initializes the SPI status struct. 215 * 216 * \param spi_mode Specifies if USI should trigger on positive (0) or negative 217 * (1) edge of clock signal 218 * 219 * \note Clears the stored data 220 * 221 * \todo Timer should reset SPI protocol on timeout 222 */ \ In segment CODE, align 2, keep-with-next 223 void SPI_Init(unsigned char spi_mode) \ SPI_Init: 224 { 225 __disable_interrupt(); \ 00000000 94F8 CLI 226 227 // Configure outputs and inputs, enable pull-ups for DATAIN and CLOCK pins. 228 USI_DIR_REG |= (1<> 8 \ 0000001C E000 LDI R16, 0 \ 0000001E 8300 ST Z, R16 237 SPI.State = ST_CMD; // Initial SPI state: wait for command. 238 SPI.Read = FALSE; // Doesn't matter right now. 239 SPI.EEPROM = FALSE; // Doesn't matter right now. \ 00000020 8103 LDD R16, Z+3 \ 00000022 7F0C ANDI R16, 0xFC \ 00000024 8303 STD Z+3, R16 240 SPI.Count = 0; // Doesn't matter right now. \ 00000026 E400 LDI R16, 64 \ 00000028 8302 STD Z+2, R16 241 SPI.Address = 0; // Doesn't matter right now. \ 0000002A E000 LDI R16, 0 \ 0000002C 8301 STD Z+1, R16 242 SPI.XferComplete = FALSE; // We haven't even started a transfer yet. 243 SPI.WriteCollision = FALSE; // ..And therefore a collision hasn't happened. \ 0000002E 8103 LDD R16, Z+3 \ 00000030 7F03 ANDI R16, 0xF3 \ 00000032 8303 STD Z+3, R16 244 245 __enable_interrupt(); \ 00000034 9478 SEI 246 } \ 00000036 9508 RET \ 00000038 REQUIRE _A_PORTB \ 00000038 REQUIRE _A_DDRB \ 00000038 REQUIRE _A_USICR 247 248 249 // Put one byte on bus. Use this function like you would write to the SPDR 250 // register in the native SPI module. Calling this function will prepare a 251 // byte for the next transfer initiated by the master device. If a transfer 252 // is in progress, this function will set the write collision flag and return 253 // without altering the data registers. 254 // 255 // Returns 0 if a write collision occurred, 1 otherwise. 256 /*! \brief Write a byte to SPI bus 257 * 258 * This function first checks if a transmission is in progress, and if so, flags 259 * a write collision, and returns FALSE.\n 260 * If a transmission is not in progress, the flags for write collision and 261 * transfer complete are cleared, and the input byte is written to SPDR.\n 262 * 263 * \param val The byte to send. 264 * 265 * \retval FALSE A write collision happened. 266 * \retval TRUE Byte written to SPDR. 267 */ \ In segment CODE, align 2, keep-with-next 268 unsigned char SPI_Put(unsigned char val) \ SPI_Put: 269 { 270 // Check if transmission in progress, i.e. if USI counter doesn't equal zero. 271 // If this fails, flag a write collision and return. 272 if((USISR & 0x0F) != 0) { \ 00000000 B11E IN R17, 0x0E \ 00000002 701F ANDI R17, 0x0F \ 00000004 .... LDI R30, LOW(SPI) \ 00000006 .... LDI R31, (SPI) >> 8 \ 00000008 F029 BREQ ??SPI_Put_0 273 SPI.WriteCollision = TRUE; \ 0000000A 8103 LDD R16, Z+3 \ 0000000C 6008 ORI R16, 0x08 \ 0000000E 8303 STD Z+3, R16 274 return(FALSE); \ 00000010 E000 LDI R16, 0 \ 00000012 9508 RET 275 } 276 277 // Reinitialize flags. 278 SPI.XferComplete = FALSE; 279 SPI.WriteCollision = FALSE; \ ??SPI_Put_0: \ 00000014 8113 LDD R17, Z+3 \ 00000016 7F13 ANDI R17, 0xF3 \ 00000018 8313 STD Z+3, R17 280 281 USIDR = val; // Put data in USI data register. \ 0000001A B90F OUT 0x0F, R16 282 283 return (TRUE); \ 0000001C E001 LDI R16, 1 \ 0000001E 9508 RET \ 00000020 REQUIRE _A_USIDR \ 00000020 REQUIRE _A_USISR 284 } 285 286 287 // Get one byte from bus. This function only returns the previous stored 288 // USIDR value. The transfer complete flag is not checked. Use this function 289 // like you would read from the SPDR register in the native SPI module. 290 /*! \brief Get the last byte received from SPI bus 291 * 292 * This function simply returns the last byte stored to the SPI status struct, 293 * without checking if a completed transfer is flagged. 294 * 295 * \retval SPI.Data The last byte read from SPI. 296 */ \ In segment CODE, align 2, keep-with-next 297 unsigned char SPI_Get(void) \ SPI_Get: 298 { 299 return SPI.Data; \ 00000000 9100.... LDS R16, SPI \ 00000004 9508 RET 300 } 301 302 303 /*! \brief Wait for SPI transfer to complete 304 * 305 * This function waits for a transfer complete to be flagged. 306 */ \ In segment CODE, align 2, keep-with-next 307 void SPI_Wait(void) \ SPI_Wait: 308 { \ 00000000 9100.... LDS R16, (SPI + 3) \ 00000004 FF02 SBRS R16, 2 309 do { // Wait for transfer complete. 310 } while (SPI.XferComplete == FALSE); \ ??SPI_Wait_0: \ 00000006 CFFF RJMP ??SPI_Wait_0 311 } \ ??SPI_Wait_1: \ 00000008 9508 RET \ In segment INTVEC, offset 0x10, root \ `??USI_OVF_ISR??INTVEC 16`: \ 00000010 .... RJMP USI_OVF_ISR Maximum stack usage in bytes: Function CSTACK RSTACK -------- ------ ------ SPI_Get 0 2 SPI_Init 0 2 SPI_Put 0 2 SPI_Wait 0 2 USI_OVF_ISR 15 4 -> Time_Left 15 2 -> Time_Set 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 -> SPI_Put 15 2 Segment part sizes: Function/Label Bytes -------------- ----- _A_PORTB 1 _A_DDRB 1 _A_USIDR 1 _A_USISR 1 _A_USICR 1 SPI 4 USI_OVF_ISR 366 SPI_Init 56 SPI_Put 32 SPI_Get 6 SPI_Wait 10 ??USI_OVF_ISR??INTVEC 16 2 Others 6 5 bytes in segment ABSOLUTE 470 bytes in segment CODE 6 bytes in segment INITTAB 2 bytes in segment INTVEC 4 bytes in segment NEAR_Z 470 bytes of CODE memory (+ 8 bytes shared) 4 bytes of DATA memory (+ 5 bytes shared) Errors: none Warnings: none