4008-04-07 Release

[avr_bc100.git] / BaseMegaFirmware / GCC / bc100_slave.c

diff --git a/BaseMegaFirmware/GCC/bc100_slave.c b/BaseMegaFirmware/GCC/bc100_slave.c
new file mode 100644 (file)
index 0000000..a03a334
--- /dev/null
+++ b/BaseMegaFirmware/GCC/bc100_slave.c
@@ -0,0 +1,105 @@
+// Martin Thomas 3/2008\r
+\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+#include <avr/io.h>\r
+\r
+#include "../../BaseTinyFirmware/GCC/enums.h"\r
+#include "../../BaseTinyFirmware/GCC/structs.h"\r
+\r
+#include "spi.h"\r
+#include "bc100_slave.h"\r
+\r
+#ifdef BC100_SLAVE_TEST\r
+#include "mystdio.h"\r
+#endif\r
+\r
+#define dummy 0x00\r
+\r
+void bc100_slave_init( void )\r
+{\r
+}\r
+\r
+uint8_t bc100_slave_read( uint8_t cmd, size_t size, void *buf )\r
+{\r
+       uint8_t err = 0;\r
+\r
+       return err;\r
+}\r
+\r
+#ifdef BC100_SLAVE_TEST\r
+\r
+uint8_t bc100_slave_test(void)\r
+{\r
+       uint8_t err = 0;\r
+       uint8_t in, out, i;\r
+       uint32_t timevals[TIMERS];\r
+\r
+       SPI_init();\r
+\r
+       SPI_rw( dummy );\r
+       myprintf_P("Timers:\n");\r
+       out = BC100_SLAVE_READ | BC100_SLAVE_SRAM | sizeof(timevals);\r
+       SPI_rw( out );\r
+       out = ADR_TIMERS;\r
+       in = SPI_rw( out );\r
+       myprintf_P("In1 : 0x%02x (expected 0xcc)\n", in );\r
+       in = SPI_rw( dummy );\r
+       myprintf_P("In2 : 0x%02x (expected 0xbb)\n", in );\r
+#if 0\r
+       uint8_t tmp\r
+       for ( i = TIMERS; i > 0; i-- ) {\r
+               tmp  = (uint32_t)(SPI_rw(dummy)) << 24;\r
+               tmp |= (uint32_t)(SPI_rw(dummy)) << 16;\r
+               tmp |= (uint32_t)(SPI_rw(dummy)) <<  8;\r
+               tmp |= (uint32_t)(SPI_rw(dummy)) <<  0;\r
+               timevals[i-1] = tmp;\r
+       }\r
+#else\r
+       i = sizeof(timevals);\r
+       while ( i-- > 0 ) {\r
+               *( (unsigned char*)&timevals + i ) = SPI_rw(dummy);\r
+       }\r
+#endif\r
+       for ( i=0; i<TIMERS; i++ ) {\r
+               myprintf_P("Timer #%d = %lu (0x%08lx)\n", i, timevals[i], timevals[i] );\r
+       }\r
+\r
+\r
+       ADC_Status_t ADCS;\r
+       myprintf_P("ADC-Status:\n");\r
+       out = BC100_SLAVE_READ | BC100_SLAVE_SRAM | sizeof(ADCS);\r
+       SPI_rw( out );\r
+       out = ADR_ADCS;\r
+       in = SPI_rw( out );\r
+       myprintf_P("In1 : 0x%02x (expected 0xcc)\n", in );\r
+       in = SPI_rw( dummy );\r
+       myprintf_P("In2 : 0x%02x (expected 0xbb)\n", in );\r
+       i = sizeof(ADCS);\r
+       while ( i-- > 0 ) {\r
+               *( (unsigned char*)&ADCS + i ) = SPI_rw(dummy);\r
+       }\r
+       myprintf_P("ADC-MUX        %d\n", ADCS.MUX );\r
+       myprintf_P("Cycle complete %d\n", ADCS.Flag);\r
+       myprintf_P("Mains OK       %d\n", ADCS.Mains);\r
+       myprintf_P("A/D halt       %d\n", ADCS.Halt);\r
+       myprintf_P("Offs ADC3 g20  %d\n", ADCS.ADC3_G20_OS);\r
+       myprintf_P("Offs ADC5 g20  %d\n", ADCS.ADC5_G20_OS);\r
+       myprintf_P("rawRID         %d\n", ADCS.rawRID);\r
+       myprintf_P("rawNTC         %d\n", ADCS.rawNTC);\r
+       myprintf_P("rawVBAT        %d\n", ADCS.rawVBAT);\r
+       myprintf_P("Supply         %d [mV]\n", ADCS.VIN);\r
+       myprintf_P("Batt. Voltage  %d [mV]\n", ADCS.VBAT);\r
+       myprintf_P("Batt. Current  %d [mA]\n", ADCS.IBAT);\r
+       for ( i=0; i<4; i++ ) {\r
+               myprintf_P("DiscIBAT[%d]    %d [mA]\n", i, ADCS.discIBAT[i] );\r
+       }\r
+       myprintf_P("average IBAT   %d [mA]\n", ADCS.avgIBAT);\r
+\r
+       SPI_release();\r
+\r
+       return err;\r
+}\r
+\r
+#endif /* BC100_SLAVE_TEST */\r
+\r