* settings and supported devices see readme.html\r
*\r
* \author\r
* Atmel Corporation: http://www.atmel.com \n\r
* Support email: avr@atmel.com\r
*\r
* settings and supported devices see readme.html\r
*\r
* \author\r
* Atmel Corporation: http://www.atmel.com \n\r
* Support email: avr@atmel.com\r
*\r
{\r
// Clear OC1B on compare match, enable PWM on comparator OCR1B.\r
TCCR1A = (1<<COM1B1)|(0<<COM1B0)|(1<<PWM1B);\r
{\r
// Clear OC1B on compare match, enable PWM on comparator OCR1B.\r
TCCR1A = (1<<COM1B1)|(0<<COM1B0)|(1<<PWM1B);\r
// Copy shadow bits, disconnect OC1D.\r
TCCR1C = (TCCR1A & 0xF0);\r
// Copy shadow bits, disconnect OC1D.\r
TCCR1C = (TCCR1A & 0xF0);\r
// No fault protection, use phase & frequency correct PWM.\r
TCCR1D = (0<<WGM11)|(1<WGM10);\r
// No fault protection, use phase & frequency correct PWM.\r
TCCR1D = (0<<WGM11)|(1<WGM10);\r
// Enable PLL, use full speed mode.\r
PLLCSR = (0<<LSM) | (1<<PLLE);\r
// Enable PLL, use full speed mode.\r
PLLCSR = (0<<LSM) | (1<<PLLE);\r
// Use general timer and wait 1 ms for PLL lock to settle.\r
Time_Set(TIMER_GEN,0,0,1);\r
// Use general timer and wait 1 ms for PLL lock to settle.\r
Time_Set(TIMER_GEN,0,0,1);\r
* \retval TRUE Success, duty cycle could be decremented.\r
* \retval FALSE Failure, duty cycle already at zero.\r
*/\r
* \retval TRUE Success, duty cycle could be decremented.\r
* \retval FALSE Failure, duty cycle already at zero.\r
*/\r