r11571: fix div by zero

[cluck.git] / cluck.lisp

diff --git a/cluck.lisp b/cluck.lisp
index dff957e8d377fcc501e3c257c9d05079bd4e4aa3..1267bd15e737c0c4ad21ce28647ff7a6412fe61a 100644 (file)
--- a/cluck.lisp
+++ b/cluck.lisp
@@ -38,7 +38,7 @@
 
 (defpackage #:cluck
   (:use #:cl)
-  (:export 
+  (:export
    #:show-timers
    #:show-8-bit-timers
    #:show-16-bit-timers
@@ -57,7 +57,7 @@
 
 (defvar *base-error-zero-baud-clk* (* 9 25 8192)
 "Base multiple for multi-megahertz clock frequencies to have
-0% error at common UART baud rates. Value of this base is 1.8432 million. 
+0% error at common UART baud rates. Value of this base is 1.8432 million.
 Common multiples of this are 2 (3.6864Mhz), 4 (7.3728Mhz), 8 (14745600),
 and 10 (18.432MHz)")
 
@@ -126,9 +126,9 @@ controllers, 32-bit timers use 8-bit prescalers"
 rates for F_CPU. UBBR is limited to 12 bits."
   (dolist (baud *baud-rates*)
     (let* ((ubrr (min 4096
-                      (round (- (/ f-cpu 16 baud) 1))))
+                      (max 0 (round (- (/ f-cpu 16 baud) 1)))))
            (ubrr2 (min 4096
-                       (round (- (/ f-cpu 8 baud) 1))))
+                       (max 0 (round (- (/ f-cpu 8 baud) 1)))))
            (actual-baud (/ f-cpu 16 (1+ ubrr)))
            (actual-baud2 (/ f-cpu 8 (1+ ubrr2)))
            (err (* 100 (- (/ actual-baud baud) 1)))
@@ -144,10 +144,10 @@ rates for F_CPU. UBBR is limited to 12 bits."
 rates for Fcy. BRG is limited to 16 bits."
   (dolist (baud *baud-rates*)
     (let* ((brg (min 65536
-                     (max 1 (round (- (/ fcy 16 baud) 1)))))
+                     (max 0 (round (- (/ fcy 16 baud) 1)))))
            (actual-baud (/ fcy 16 (1+ brg)))
            (err (* 100 (- (/ actual-baud baud) 1))))
-      (when (or (not view-below-percent) 
+      (when (or (not view-below-percent)
                 (< (abs err) view-below-percent))
         (format t "~6D ~4D ~5,1F%~%" baud brg err)))))