BaseTinyFirmware/IAR/Debug/List/PWM.s90

   1 ///////////////////////////////////////////////////////////////////////////////\r
   2 //                                                                            /\r
   3 // IAR Atmel AVR C/C++ Compiler V4.30F/W32              12/Mar/2008  23:01:38 /\r
   4 // Copyright 1996-2007 IAR Systems. All rights reserved.                      /\r
   5 //                                                                            /\r
   6 //    Source file  =  C:\home\kevin\pub\src\bc100_cal\IAR\PWM.c               /\r
   7 //    Command line =  C:\home\kevin\pub\src\bc100_cal\IAR\PWM.c               /\r
   8 //                    --cpu=tiny861 -ms -o C:\home\kevin\pub\src\bc100_cal\IA /\r
   9 //                    R\Debug\Obj\ -lC C:\home\kevin\pub\src\bc100_cal\IAR\De /\r
  10 //                    bug\List\ -lB C:\home\kevin\pub\src\bc100_cal\IAR\Debug /\r
  11 //                    \List\ --initializers_in_flash -z2 --no_cse             /\r
  12 //                    --no_inline --no_code_motion --no_cross_call            /\r
  13 //                    --no_clustering --no_tbaa --debug                       /\r
  14 //                    -DENABLE_BIT_DEFINITIONS -e --require_prototypes -I     /\r
  15 //                    "C:\Program Files\IAR Systems\Embedded Workbench        /\r
  16 //                    4.0\avr\INC\" -I "C:\Program Files\IAR                  /\r
  17 //                    Systems\Embedded Workbench 4.0\avr\INC\CLIB\"           /\r
  18 //                    --eeprom_size 512                                       /\r
  19 //    List file    =  C:\home\kevin\pub\src\bc100_cal\IAR\Debug\List\PWM.s90  /\r
  20 //                                                                            /\r
  21 //                                                                            /\r
  22 ///////////////////////////////////////////////////////////////////////////////\r
  23 \r
  24         NAME PWM\r
  25 \r
  26         RSEG CSTACK:DATA:NOROOT(0)\r
  27         RSEG RSTACK:DATA:NOROOT(0)\r
  28 \r
  29         PUBLIC PWM_DecrementDutyCycle\r
  30         PUBLIC PWM_IncrementDutyCycle\r
  31         PUBLIC PWM_Start\r
  32         PUBLIC PWM_Stop\r
  33         PUBWEAK _A_DDRB\r
  34         PUBWEAK _A_DT1\r
  35         PUBWEAK _A_OCR1A\r
  36         PUBWEAK _A_OCR1B\r
  37         PUBWEAK _A_OCR1C\r
  38         PUBWEAK _A_OCR1D\r
  39         PUBWEAK _A_PLLCSR\r
  40         PUBWEAK _A_TCCR1A\r
  41         PUBWEAK _A_TCCR1B\r
  42         PUBWEAK _A_TCCR1C\r
  43         PUBWEAK _A_TCCR1D\r
  44         PUBWEAK _A_TCCR1E\r
  45         PUBWEAK __?EEARH\r
  46         PUBWEAK __?EEARL\r
  47         PUBWEAK __?EECR\r
  48         PUBWEAK __?EEDR\r
  49 \r
  50         EXTERN Time_Set\r
  51         EXTERN Time_Left\r
  52 \r
  53 // C:\home\kevin\pub\src\bc100_cal\IAR\PWM.c\r
  54 //    1 /* This file has been prepared for Doxygen automatic documentation generation.*/\r
  55 //    2 /*! \file *********************************************************************\r
  56 //    3  *\r
  57 //    4  * \brief\r
  58 //    5  *      Functions for use of PWM\r
  59 //    6  *\r
  60 //    7  *      Contains functions for initializing and controlling PWM output.\r
  61 //    8  *\r
  62 //    9  * \par Application note:\r
  63 //   10  *      AVR458: Charging Li-Ion Batteries with BC100\n\r
  64 //   11  *      AVR463: Charging NiMH Batteries with BC100\r
  65 //   12  *\r
  66 //   13  * \par Documentation\r
  67 //   14  *      For comprehensive code documentation, supported compilers, compiler \r
  68 //   15  *      settings and supported devices see readme.html\r
  69 //   16  *\r
  70 //   17  * \author\r
  71 //   18  *      Atmel Corporation: http://www.atmel.com \n\r
  72 //   19  *      Support email: avr@atmel.com\r
  73 //   20  *\r
  74 //   21  * \r
  75 //   22  * $Name$\r
  76 //   23  * $Revision: 2299 $\r
  77 //   24  * $RCSfile$\r
  78 //   25  * $URL: http://svn.norway.atmel.com/AppsAVR8/avr458_Charging_Li-Ion_Batteries_with_BC100/tag/20070904_release_1.0/code/IAR/PWM.c $\r
  79 //   26  * $Date: 2007-08-23 12:55:51 +0200 (to, 23 aug 2007) $\n\r
  80 //   27  ******************************************************************************/\r
  81 //   28 \r
  82 //   29 #include <ioavr.h>\r
  83 \r
  84         ASEGN ABSOLUTE:DATA:NOROOT,050H\r
  85 // <unnamed> volatile __io _A_TCCR1A\r
  86 _A_TCCR1A:\r
  87         DS 1\r
  88 \r
  89         ASEGN ABSOLUTE:DATA:NOROOT,04fH\r
  90 // <unnamed> volatile __io _A_TCCR1B\r
  91 _A_TCCR1B:\r
  92         DS 1\r
  93 \r
  94         ASEGN ABSOLUTE:DATA:NOROOT,04dH\r
  95 // <unnamed> volatile __io _A_OCR1A\r
  96 _A_OCR1A:\r
  97         DS 1\r
  98 \r
  99         ASEGN ABSOLUTE:DATA:NOROOT,04cH\r
 100 // <unnamed> volatile __io _A_OCR1B\r
 101 _A_OCR1B:\r
 102         DS 1\r
 103 \r
 104         ASEGN ABSOLUTE:DATA:NOROOT,04bH\r
 105 // <unnamed> volatile __io _A_OCR1C\r
 106 _A_OCR1C:\r
 107         DS 1\r
 108 \r
 109         ASEGN ABSOLUTE:DATA:NOROOT,04aH\r
 110 // <unnamed> volatile __io _A_OCR1D\r
 111 _A_OCR1D:\r
 112         DS 1\r
 113 \r
 114         ASEGN ABSOLUTE:DATA:NOROOT,049H\r
 115 // <unnamed> volatile __io _A_PLLCSR\r
 116 _A_PLLCSR:\r
 117         DS 1\r
 118 \r
 119         ASEGN ABSOLUTE:DATA:NOROOT,047H\r
 120 // <unnamed> volatile __io _A_TCCR1C\r
 121 _A_TCCR1C:\r
 122         DS 1\r
 123 \r
 124         ASEGN ABSOLUTE:DATA:NOROOT,046H\r
 125 // <unnamed> volatile __io _A_TCCR1D\r
 126 _A_TCCR1D:\r
 127         DS 1\r
 128 \r
 129         ASEGN ABSOLUTE:DATA:NOROOT,044H\r
 130 // <unnamed> volatile __io _A_DT1\r
 131 _A_DT1:\r
 132         DS 1\r
 133 \r
 134         ASEGN ABSOLUTE:DATA:NOROOT,037H\r
 135 // <unnamed> volatile __io _A_DDRB\r
 136 _A_DDRB:\r
 137         DS 1\r
 138 \r
 139         ASEGN ABSOLUTE:DATA:NOROOT,020H\r
 140 // <unnamed> volatile __io _A_TCCR1E\r
 141 _A_TCCR1E:\r
 142         DS 1\r
 143 //   30 \r
 144 //   31 #include "enums.h"\r
 145 //   32 \r
 146 //   33 #include "main.h"\r
 147 //   34 #include "PWM.h"\r
 148 //   35 #include "time.h"\r
 149 //   36 \r
 150 //   37 \r
 151 //   38 //******************************************************************************\r
 152 //   39 // Functions\r
 153 //   40 //******************************************************************************\r
 154 //   41 /*! \brief Stops PWM output\r
 155 //   42  *\r
 156 //   43  */\r
 157 \r
 158         RSEG CODE:CODE:NOROOT(1)\r
 159 //   44 void PWM_Stop(void)\r
 160 PWM_Stop:\r
 161 //   45 {\r
 162 //   46         OCR1B = 0;  // Reset compare level.\r
 163         LDI     R16, 0\r
 164         OUT     0x2C, R16\r
 165 //   47         PLLCSR = 0; // Disable PLL, switch to synchronous CLK mode.\r
 166         LDI     R16, 0\r
 167         OUT     0x29, R16\r
 168 //   48         TCCR1A = 0; // Set normal port operation, disable PWM modes.\r
 169         LDI     R16, 0\r
 170         OUT     0x30, R16\r
 171 //   49         TCCR1B = 0; // Stop timer/counter1.\r
 172         LDI     R16, 0\r
 173         OUT     0x2F, R16\r
 174 //   50         TCCR1C = 0; // Set normal port operation.\r
 175         LDI     R16, 0\r
 176         OUT     0x27, R16\r
 177 //   51         TCCR1D = 0; // No fault protection, normal waveform.\r
 178         LDI     R16, 0\r
 179         OUT     0x26, R16\r
 180 //   52         OCR1C = 0;  // Reset compare.\r
 181         LDI     R16, 0\r
 182         OUT     0x2B, R16\r
 183 //   53         OCR1D = 0;  // Reset compare.\r
 184         LDI     R16, 0\r
 185         OUT     0x2A, R16\r
 186 //   54         DT1 = 0;    // No dead time values.\r
 187         LDI     R16, 0\r
 188         OUT     0x24, R16\r
 189 //   55 }\r
 190         RET\r
 191         REQUIRE _A_TCCR1A\r
 192         REQUIRE _A_TCCR1B\r
 193         REQUIRE _A_OCR1B\r
 194         REQUIRE _A_OCR1C\r
 195         REQUIRE _A_OCR1D\r
 196         REQUIRE _A_PLLCSR\r
 197         REQUIRE _A_TCCR1C\r
 198         REQUIRE _A_TCCR1D\r
 199         REQUIRE _A_DT1\r
 200 //   56 \r
 201 //   57 \r
 202 //   58 /*! \brief Initializes and starts PWM output\r
 203 //   59  *\r
 204 //   60  * Initializes timer1 for use as a PWM with a clock rate of 64 MHz.\n\r
 205 //   61  * Its comparator is connected to PB3 and will output high until timer1 reaches\r
 206 //   62  * the value of OCR1B. It is then dropped to 0.\n\r
 207 //   63  * The comparator outputs high again when the counter overflows, which will\r
 208 //   64  * happen at a rate of 250 kHz.\r
 209 //   65  */\r
 210 \r
 211         RSEG CODE:CODE:NOROOT(1)\r
 212 //   66 void PWM_Start(void)\r
 213 PWM_Start:\r
 214 //   67 {\r
 215 //   68         // Clear OC1B on compare match, enable PWM on comparator OCR1B.\r
 216 //   69         TCCR1A = (1<<COM1B1)|(0<<COM1B0)|(1<<PWM1B);\r
 217         LDI     R16, 33\r
 218         OUT     0x30, R16\r
 219 //   70         \r
 220 //   71         // Non-inverted PWM, T/C stopped.\r
 221 //   72         TCCR1B = 0;\r
 222         LDI     R16, 0\r
 223         OUT     0x2F, R16\r
 224 //   73         \r
 225 //   74         // Copy shadow bits, disconnect OC1D.\r
 226 //   75         TCCR1C = (TCCR1A & 0xF0);\r
 227         IN      R16, 0x30\r
 228         ANDI    R16, 0xF0\r
 229         OUT     0x27, R16\r
 230 //   76         \r
 231 //   77         // No fault protection, use phase & frequency correct PWM.\r
 232 //   78         TCCR1D = (0<<WGM11)|(1<WGM10);\r
 233         LDI     R16, 0\r
 234         OUT     0x26, R16\r
 235 //   79         \r
 236 //   80         // Does not matter -- PWM6 mode not used.\r
 237 //   81         TCCR1E = 0;\r
 238         LDI     R16, 0\r
 239         OUT     0x00, R16\r
 240 //   82         \r
 241 //   83         // Does not matter -- OC1A is disabled.\r
 242 //   84         OCR1A = 0;\r
 243         LDI     R16, 0\r
 244         OUT     0x2D, R16\r
 245 //   85         \r
 246 //   86         // Set reset compare level. (Offset is used, or JumperCheck() will fail.)\r
 247 //   87         OCR1B = PWM_OFFSET;\r
 248         LDI     R16, 12\r
 249         OUT     0x2C, R16\r
 250 //   88         \r
 251 //   89         // TOP value for PWM, f(PWM) = 64MHz / 255 = 251kHz.\r
 252 //   90         OCR1C = 0xFF;\r
 253         LDI     R16, 255\r
 254         OUT     0x2B, R16\r
 255 //   91         \r
 256 //   92         // Does not matter -- OC1D is disabled.\r
 257 //   93         OCR1D = 0;\r
 258         LDI     R16, 0\r
 259         OUT     0x2A, R16\r
 260 //   94         \r
 261 //   95         // No dead time values.\r
 262 //   96         DT1 = 0;\r
 263         LDI     R16, 0\r
 264         OUT     0x24, R16\r
 265 //   97         \r
 266 //   98         // Set PWM port pin to output.\r
 267 //   99         DDRB |= (1<<PB3);\r
 268         SBI     0x17, 0x03\r
 269 //  100         \r
 270 //  101         // Enable PLL, use full speed mode.\r
 271 //  102         PLLCSR = (0<<LSM) | (1<<PLLE);\r
 272         LDI     R16, 2\r
 273         OUT     0x29, R16\r
 274 //  103         \r
 275 //  104         // Use general timer and wait 1 ms for PLL lock to settle.\r
 276 //  105         Time_Set(TIMER_GEN,0,0,1);\r
 277         LDI     R20, 1\r
 278         LDI     R17, 0\r
 279         LDI     R18, 0\r
 280         LDI     R19, 0\r
 281         LDI     R16, 2\r
 282         RCALL   Time_Set\r
 283 //  106         do{ \r
 284 //  107         }while(Time_Left(TIMER_GEN));\r
 285 ??PWM_Start_0:\r
 286         LDI     R16, 2\r
 287         RCALL   Time_Left\r
 288         TST     R16\r
 289         BRNE    ??PWM_Start_0\r
 290 //  108         \r
 291 //  109         // Now wait for PLL to lock.\r
 292 //  110         do{ \r
 293 //  111         }while((PLLCSR & (1<<PLOCK)) == 0);\r
 294 ??PWM_Start_1:\r
 295         IN      R16, 0x29\r
 296         MOV     R17, R16\r
 297         SBRS    R17, 0\r
 298         RJMP    ??PWM_Start_1\r
 299 //  112 \r
 300 //  113         // Use PLL as clock source.\r
 301 //  114         PLLCSR |= (1<<PCKE);\r
 302         IN      R16, 0x29\r
 303         ORI     R16, 0x04\r
 304         OUT     0x29, R16\r
 305 //  115         \r
 306 //  116         // CLK PCK = 64MHz / 1 = 64MHz.\r
 307 //  117         TCCR1B |= (0<<CS13)|(0<<CS12)|(0<<CS11)|(1<<CS10);\r
 308         IN      R16, 0x2F\r
 309         ORI     R16, 0x01\r
 310         OUT     0x2F, R16\r
 311 //  118 }\r
 312         RET\r
 313         REQUIRE _A_TCCR1A\r
 314         REQUIRE _A_TCCR1B\r
 315         REQUIRE _A_OCR1A\r
 316         REQUIRE _A_OCR1B\r
 317         REQUIRE _A_OCR1C\r
 318         REQUIRE _A_OCR1D\r
 319         REQUIRE _A_PLLCSR\r
 320         REQUIRE _A_TCCR1C\r
 321         REQUIRE _A_TCCR1D\r
 322         REQUIRE _A_DT1\r
 323         REQUIRE _A_DDRB\r
 324         REQUIRE _A_TCCR1E\r
 325 //  119 \r
 326 //  120 \r
 327 //  121 /*! \brief Increments the PWM duty cycle, if not already at max\r
 328 //  122  *\r
 329 //  123  * \retval TRUE Success, duty cycle could be incremented.\r
 330 //  124  * \retval FALSE Failure, duty cycle already at maximum.\r
 331 //  125  */\r
 332 \r
 333         RSEG CODE:CODE:NOROOT(1)\r
 334 //  126 unsigned char PWM_IncrementDutyCycle(void){\r
 335 PWM_IncrementDutyCycle:\r
 336 //  127 \r
 337 //  128         if (OCR1B < PWM_MAX) {\r
 338         IN      R16, 0x2C\r
 339         CPI     R16, 255\r
 340         BRCC    ??PWM_IncrementDutyCycle_0\r
 341 //  129                 OCR1B += 1;\r
 342         IN      R16, 0x2C\r
 343         INC     R16\r
 344         OUT     0x2C, R16\r
 345 //  130                 return(TRUE);\r
 346         LDI     R16, 1\r
 347         RET\r
 348 //  131         } else {\r
 349 //  132                 return(FALSE);\r
 350 ??PWM_IncrementDutyCycle_0:\r
 351         LDI     R16, 0\r
 352         RET\r
 353         REQUIRE _A_OCR1B\r
 354 //  133         }\r
 355 //  134 }\r
 356 //  135 \r
 357 //  136 \r
 358 //  137 /*! \brief Decrements the PWM duty cycle, if not already at zero.\r
 359 //  138  *\r
 360 //  139  * \retval TRUE Success, duty cycle could be decremented.\r
 361 //  140  * \retval FALSE Failure, duty cycle already at zero.\r
 362 //  141  */\r
 363 \r
 364         RSEG CODE:CODE:NOROOT(1)\r
 365 //  142 unsigned char PWM_DecrementDutyCycle(void){\r
 366 PWM_DecrementDutyCycle:\r
 367 //  143         \r
 368 //  144         if (OCR1B > 0)  {\r
 369         IN      R16, 0x2C\r
 370         CPI     R16, 1\r
 371         BRCS    ??PWM_DecrementDutyCycle_0\r
 372 //  145                 OCR1B -= 1;\r
 373         IN      R16, 0x2C\r
 374         DEC     R16\r
 375         OUT     0x2C, R16\r
 376 //  146                 return(TRUE);\r
 377         LDI     R16, 1\r
 378         RET\r
 379 //  147         } else {\r
 380 //  148                 return(FALSE);\r
 381 ??PWM_DecrementDutyCycle_0:\r
 382         LDI     R16, 0\r
 383         RET\r
 384         REQUIRE _A_OCR1B\r
 385 //  149         }\r
 386 //  150 }\r
 387 \r
 388         ASEGN ABSOLUTE:DATA:NOROOT,01cH\r
 389 __?EECR:\r
 390 \r
 391         ASEGN ABSOLUTE:DATA:NOROOT,01dH\r
 392 __?EEDR:\r
 393 \r
 394         ASEGN ABSOLUTE:DATA:NOROOT,01eH\r
 395 __?EEARL:\r
 396 \r
 397         ASEGN ABSOLUTE:DATA:NOROOT,01fH\r
 398 __?EEARH:\r
 399 \r
 400         END\r
 401 // \r
 402 //  12 bytes in segment ABSOLUTE\r
 403 // 168 bytes in segment CODE\r
 404 // \r
 405 // 168 bytes of CODE memory\r
 406 //   0 bytes of DATA memory (+ 12 bytes shared)\r
 407 //\r
 408 //Errors: none\r
 409 //Warnings: none\r